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CCSDS-RS(255,223)码高速译码器的硬件实现研究

张拯宁;李集林;战勇杰;刘长柱;   

  1. 中国空间技术研究院航天恒星科技有限公司;北京遥感信息技术研究所;
  • 发布日期:2009-10-25

Research on the Implementation of CCSDS-RS(255,223) High Speed Decoder

Zhang Zhengning1 Li Jilin1 Zhan Yongjie1 Liu Changzhu2(1 Space Star Technology Co.,Ltd,Beijing 100086)(2 Beijing Remote Sensing Information Institute,Beijing 100086)   

  • Online:2009-10-25

摘要: 研究了空间通信用高速Reed-Solomon(255,223)码硬判决译码器的FPGA实现方法,提出一种新的纠错算法实现结构以最大程度提高译码器性能。设计中采用RiBM算法求解关键方程,并通过应用高速比特并行乘法器以及流水线和并行处理方法提高译码通过率。综合和测试验证结果显示,该译码器译码通过速率为1.7Gbit/s,译码延迟为296个时钟周期,优于目前同类型的RS译码器性能指标。

关键词: 译码器算法, 有限域, 里德-索洛蒙码, 空间数据系统体制, 空间通信

Abstract: Reed-Solomon(RS) code is a linear block code which has very strong capability of correcting random or burst errors.It has been widely used in various communication systems.A FPGA implementation of high speed RS(255,223) decoder used for space communication was presented and a new high speed error-correct architecture which using RiBM algorithm to solve the key equation for decoding Reed-Solomon codes was given.Moreover,high speed bit parallel Galois field multiplier and pipelining methods were used to achieve maximum decoding speed.Synthesis and experiments results show that the FPGA implementation of the decoder achieves a throughput of 1.7Gbit/s and decode delay of 296 clocks,the performance is multiple times higher than conventional design′s.