高速RS编码器的FPGA实现

• •

高速RS编码器的FPGA实现

于伟,李文,鞠德航

西安空间无线电技术研究所!西安710000,西安空间无线电技术研究所!西安710000,西安空间无线电技术研究所!西安710000

发布日期:1999-08-25

Implem entation of R S Code with FPGA

Yu Wei Li Wen Ju Dehang( Xi'an Institute of Space Radio Technology, Xi'an 710000)

Published:1999-08-25

摘要/Abstract

摘要： ＲＳ码广泛应用于卫星通信、移动通信和数据存储等领域中。研究用现场可编程逻辑阵列（ＦＰＧＡ）实现高速ＲＳ码编码器；对硬件实现中的主要问题做了分析和讨论。仿真和实际测试结果均表明，编码器原理样机功能正常，吞吐率可达２００Ｍｂｉｔ／ｓ。

关键词: 可编程逻辑阵列;编码器;设计;实时仿真

Abstract: A high speed Reed Solom on ( R S) encoder prototype is im plem ented w ith F P G A ( Field Program m able Gate Array). Som e key points in the design ofthe R Sencoderhardw are are discussed. The results obtained by test and tim ing sim ulation show that thethroughput of the prototype can be up to 200 Mbit/s.

于伟,李文,鞠德航. 高速RS编码器的FPGA实现[J]. .

Yu Wei Li Wen Ju Dehang( Xi'an Institute of Space Radio Technology, Xi'an 710000). Implem entation of R S Code with FPGA[J]. .