Abstract: A new method to mitigate SEU on FPGA based-on SRAM,named DMRC,was proposed by analyzing the influences of SEU on FPGA based-on SRAM and comparing with several common mitigation techniques: Scrubbing、ECC and TMR.By validation baced-on simulation software of On-Borad FPGA,it was proved that the new method mitigating SEU on the 64-taps LFSR saved 92% redundant logic elements and shortened 26% additional delay comparing with hardware-based TMR.Thus,the method reduced greatly the cost of fault-toletant design.