Abstract: Reed-Solomon(RS) code is a linear block code which has very strong capability of correcting random or burst errors.It has been widely used in various communication systems.A FPGA implementation of high speed RS(255,223) decoder used for space communication was presented and a new high speed error-correct architecture which using RiBM algorithm to solve the key equation for decoding Reed-Solomon codes was given.Moreover,high speed bit parallel Galois field multiplier and pipelining methods were used to achieve maximum decoding speed.Synthesis and experiments results show that the FPGA implementation of the decoder achieves a throughput of 1.7Gbit/s and decode delay of 296 clocks,the performance is multiple times higher than conventional design′s.