Abstract: The traditional onboard computer time maintenance is mainly implemented by software. In order to avoid the second interrupt interval being too small or too large during the time calibration process, the software needs to perform multiple operations on the external timer Intel 82C54 chip through complicated logic and algorithms. It is very likely to make mistakes, and it takes a lot of CPU machine cycles. With the increasing tasks for spacecraft intelligent processing in the future, the CPU machine cycle becomes more and more scarce. In order to free the CPU from the cumbersome time calibration operation, a timecalibration method with controllable second interrupt interval based on FPGA was proposed. The satellite time timer was designed with the FPGA logic circuit. And the trigger condition of timecalibration was designed by using the constraint condition of second interrupt interval. When the trigger condition of timecalibration is met, the FPGA logic circuit automatically executes the timecalibration operation, which solves the problem of too large or too small second interrupt intervals during the timecalibration process, and saves a lot of CPU machine cycles. The timecalibration method proposed has been applied on several onboard computers, and has achieved the expected goal.

Key words: onboard computer, second interrupt, timecalibration, CPU, FPGA